This invention relates generally to frequency synthesizers and more particularly to a fractional-N frequency synthesizer where a voltage controlled oscillator (VCO) is controlled by a phase locked loop such that the output frequency, F.sub.out, is N times the reference frequency, F.sub.ref, divided by a frequency multiplier of value M. That is, ##EQU1## where N is the average division of the programmable divide-by-N element and M is the multiplicand of a frequency multiplier. This invention may be employed in radiotelephone communications equipment to generate one of a plurality of signals such that a group of equally spaced channels is obtained for use by the radio frequency transceiver.
One conventional method of realizing such a group of channels is to use a bank of highly stable oscillators and merely switch between the various outputs. This system is indeed feasible but would be prohibitively complex and expensive for even a few channels.
Instead of using a bank of highly stable oscillators (e.g. crystal oscillators), a single variable oscillator may be first divided by variable means and fed to one input of a phase comparison device. The other input of the phase comparison device is fed from a highly stable reference oscillator. The output of the phase comparison device may then be filtered to remove any extraneous spurious signal components and fed back to the control input of the variable oscillator. In this manner, a system is formed such that the variable oscillator will phase lock (adjust its frequency) until the phase is aligned resulting in the frequency being equal to the reference frequency times the division number. A group of equally spaced frequency channels is then realized by varying the division ratio. This approach is known as standard phase locked loop (PLL) synthesis.
A shortcoming of this method is that the channel spacing equals the reference frequency. This equality results in noise generated by the phase comparison at frequency offsets equal to the reference frequency and its harmonics. To keep the noise within acceptable limits, the filtering device between the phase comparison and the variable oscillator control input must have a bandwidth much lower than the reference frequency. This low bandwidth results in a clean output, but also slows the transient response of the synthesizer. The transient response needs to be fast in order to track out any short duration noise to the loop or to make the synthesizer useable in a frequency hopping system or to accommodate modulation of the loop.
In order to overcome this limitation, it is desirable to operate the phase detector at a frequency much higher than the desired channel spacing. Such a method has been previously described in U.S. Pat. Nos. 3,928,813; 4,609,881; and 4,816,774. This method is known as fractional N synthesis.
The basic structure of a one-accumulator fractional-N system is shown in the block diagram of FIG. 1. A VCO 101 generates an output signal which, typically is coupled to a fully programmable frequency divider 103 which has an output to a phase detector (.phi.) 105. The control input to the divider is a summation of a coarse channel setting and the output of the digital network which provides the fractional part of the division. The phase detector 105 conventionally compares the phase of the divided VCO frequency, f.sub.vco to the phase of the reference signal frequency f.sub.ref output from a reference oscillator 107 to produce a signal which is applied to a loop filter 109 and subsequently to the VCO 101 to phase-lock the VCO output signal.
The selection of the divisor value of variable frequency divider 103 is made by digital network 111 which, in previously known implementations such as described in Z-transform equivalent in U.S. Pat. No. 4,758,802, comprises a conventional adder 113, a comparator 115 (which produces a "carry out" signal when the input to the comparator 115 exceeds a given numerical value), and feedback logic 117 which subtracts the denominator (if a carry output occurs) from the digital number representation output from adder 113 and comparator 115 before applying the digital number representation to the adder 113. A second digital number representation, which in a fractional-N synthesizer is the digital equivalent of the first differential of the offset phase with respect to time (the offset frequency), is applied to another input of the digital network 111. The overall effect of the digital network 111 is to integrate the differential phase and to apply to the PLL a control signal (in the form of a carry-out digital signal) which is a first order equivalent of the phase offset. The adder 113 sums the previous contents of the adder 113 with d.theta./dt (a numerator) on each occurrence of the reference frequency signal f.sub.ref As described in U.S. Pat. No. 4,816,774, the adder 113 output is compared is compared to a number (a denominator of a desired fractional part of the divisor when the divisor of frequency divider 103, N, is expressed as a sum of R and [numerator/denominator]). If the adder 113 contents exceed the denominator then the carry output is set true and the contents of the adder is reduced by the denominator in feedback logic 117 before the next reference pulse occurs.
Shown in the Z-transform diagram of FIG. 2 is a Z-transform equivalent digital network 111' of this one accumulator system consistent with that disclosed in U.S. Pat. No. 4,758,802. The Z-transform equation for the single accumulator system is: EQU DO=Z.sup.-1 DI+Q(1-Z.sup.-1)
The Z-transform adder 201 and 205 is fed from the numerator (minus the denominator if an overflow occurs) and the previous adder contents represented by a z.sup.-1 (delay) block 203. The comparison is considered to be a digital slicer with quantization error Q added at 207. The output from adder 207 is the digital number fed back to adder 201 and the carry out signal is taken as the output signal. For Z-transform analysis, however, no difference need be made between the output and the feedback signals.
At point B an equation can be written as follows. EQU B(z)=B(z)z.sup.-1 +A(z) or B(z)=A(z)/(1-z.sup.-1)
But Data out=B(z)+Q and A(z)=Data in-B(z)-Q Substituting this in and solving for B(z) then: EQU B(z)=Data in/(2-z.sup.-1)-Q/(2-z.sup.-1)
And solving for Data out: EQU Data out=Data in/(2-z.sup.-1)+Q(1-z.sup.-1)/(2-z.sup.-1)
This equation may now be converted to the frequency domain (Note that "v" is frequency normalized to the folding frequency): EQU Mag.(Data out/Data in)=1/(5-4 cos (PI*v)).sup.1/2 EQU Mag.(Data out/Q)={(2-2 cos (PI*v))/(5-4 cos (PI*v))}.sup.1/2
Thus, the data into adder 201 is slightly low pass filtered and the quantization noise introduced by the digital network 111' is high pass filtered. The high pass filtering of the quantization noise has the effect of reducing the spurious signals occurring at the frequency of the channel-to-channel frequency spacing of the transceiver if the spurious occurs at a frequency much below the corner of the high pass. By selecting a PLL response with a low pass corner frequency much lower in frequency than the high pass corner it is possible to reject almost all of the noise. In a single accumulator system, the high pass roll-off is 20 db/decade. Thus the reference frequency must be large to push the high pass corner to large frequencies, if sufficient noise suppression is to be obtained. (Or the PLL low pass must be very low in frequency and thus lose the benefits of wide bandwidth).
The number of accumulators can theoretically be increased to any desired order. The resulting response of the high pass characteristic to the quantization noise will be the number of accumulators times 20 db/decade thereby resulting in an increased rejection of low frequency quantization noise. The accumulators have conventionally been "recombined" in what is known as a "Pascal's triangle method" as disclosed in U.S. Pat. No. 4,609,881. In general, the higher order accumulators are recombined as (1-Z.sup.-1).sup.(n-1). A two-accumulator fractional-N synthesizer is disclosed in U.S. Pat. No. 4,204,174.
Fractional-N synthesis requires the use of a large amount of digital hardware in order to generate the necessary control sequence for the phase locked loop divider. Any practical realization of a fractional-N system requires integration of the digital functions. Fractional-N synthesis also results in noise components at the channel spacing, but these components are smaller than those produced by a standard PLL. The level of noise in a fractional-N system directly depends on the rate at which the fractional process operates and the number of accumulators. Increasing the number of accumulators and the rate of operation of the fractional-N system decreases the noise components created by increasing the corner frequency and steepening the roll off.
As the rate of operation of a fractional-N system is increased the average total division within the phase locked loop, N, must be decreased. However, the noise due to phase quantization, which is proportional to the average spacing between the states, 2*(.pi./N), increases as N decreases. In addition, as more accumulators are added the instantaneous variation of the loop division ratio must be increased. These two factors cause a large percentage change in the instantaneous phase locked loop division ratio and thus in the instantaneous phase locked loop gain. This large instantaneous gain variation results in distortion of the desired phase variations in fractional-N synthesis.